Method of forming a gate insulator in group III-V nitride semiconductor devices

ABSTRACT

A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH 3 COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O 2  environment at a temperature between about 500° C. and 800° C.

FIELD OF THE INVENTION

The present invention generally relates to the manufacture ofsemiconductor devices, and more specifically to a method of forming agate insulator in semiconductor devices and, particularly, group III-Vnitride semiconductor devices.

DESCRIPTION OF THE RELATED ART

Electronic devices based on group III-V nitride compound semiconductors,and particularly gallium nitride (GaN) semiconductors, have been subjectto intensive researches and developments in the field of electronicindustry. Principal characteristics of GaN semiconductors include highelectron mobility and saturation velocity (about 2.5×10⁷ cm/s), and highbreakdown electric field (about 5×10⁶V/cm), which make the GaNsemiconductor particularly advantageous in high-power andhigh-temperature applications.

In a GaN-based semiconductor device, the GaN semiconductor layers areconventionally grown over a substrate. To ensure good performances ofthe semiconductor device, it is known that the crystalline quality ofthe GaN semiconductor layers deposited is a determining factor toelectron mobility and velocity. In addition, using an adequategate-insulating material can improve the performance of the GaNsemiconductor device by reducing the gate leakage to a minimal level. Inthis regard, many approaches are presently implemented with varioussuccesses.

One approach is to use silicon-based dielectric materials such assilicon oxide (SiO₂) or silicon nitride (Si₃N₄) to make thegate-insulating layer. A gate-insulating layer made of the silicon-baseddielectric can ensure a larger voltage swing and a higher drain currentdensity in the semiconductor device. However, a disadvantage of SiO₂ orSi₃N₄ is its relatively low dielectric constant (about 3.9 for SiO₂, andabout 7.5 for Si₃N₄), which can cause a premature breakdown of thedielectric layer when the field effect transistor is operated at a highpower voltage.

To overcome the above issues, magnesium oxide (MgO) or scandium oxide(Sc₂O₃) are also possible alternatives for the gate-insulating layer.Owing to their higher dielectric constant (9.8 for MgO and 14 forSc₂O₃), MgO and Sc₂O₃ can alleviate adverse breakdown of thegate-insulating layer under high operating power of the GaNsemiconductor device. However, these dielectric materials are subject toundesirable thermal degradation due to a high interface state density of10¹² cm⁻²-eV⁻¹. This reflects a high crystal defect density, whichseriously limits the device performance.

Another known approach uses gallium oxide (Ga₂O₃) to form thegate-insulating layer. A Ga₂O₃ gate-insulating layer can form anisovalently bonded Ga₂O₃/GaN interface, which contributes to reduce theinterfacial defect density. Additionally, Ga₂O₃ has a wide bandgap of4.7 eV and a dielectric constant of 10, which results in a highbreakdown field. These characteristics make Ga₂O₃ a good candidate forthe gate insulator of group III-V nitride semiconductor devices.However, experiments show that the Ga₂O₃ film quality, beingcharacterized by its gate leakage, breakdown field and interface statedensity, variously depends on the preparation methods implemented,typically a thermal oxidation or a deposition by sputtering, andconsequently depends on the film thickness and roughness and its postgrowth treatment. To remedy this downside, a stack structure ofSiO₂/Ga₂O₃/GaN has been proposed to improve the interfacial quality.However, it has been shown that the electrical characteristics of suchstack device structure are strictly determined by the effectivethickness of the SiO₂ layer, regardless of the presence of the Ga₂O₃interlayer. Consequently, the same issues related to SiO₂ as discussedabove can be observed in the dielectric structure SiO₂/Ga₂O₃/GaN.

The foregoing problems encountered in the prior art call for an improvedmanufacturing method capable of providing a gate-insulating layer withimproved characteristics in metal-oxide-semiconductor devices and, moreparticularly, group III-V nitride semiconductor devices.

SUMMARY OF THE INVENTION

The application describes a method of forming a gate insulator made ofan oxide compound in the manufacture of a semiconductor device.

In an embodiment, the semiconductor device is a group III-V nitridesemiconductor device and the oxide compound of the gate insulatorincludes gallium oxide formed from a gallium nitride layer of the groupIII-V nitride semiconductor device. The manufacturing method comprisesconducting a photo-assisted electrochemical process to form agate-insulating layer on the gallium nitride layer, wherein thegate-insulating layer includes gallium oxynitride and gallium oxide, andperforming a rapid thermal annealing process. The gallium oxynitride isformed with a graded composition between the n-type gallium nitridelayer and the gallium oxide layer.

In an embodiment, the photo-assisted electrochemical process includeselectrically connecting the substrate to an electrometer, immersing thesubstrate in an electrolyte bath including acetic acid (CH₃COOH), andemitting a radiation light onto the substrate. In an embodiment, theradiation light has a wavelength between about 250 nm and 260 nm.

In an embodiment, the rapid thermal annealing process is performed in O₂environment, and the rapid thermal annealing process is performed at atemperature between about 500° C. and 800° C.

The foregoing is a summary and shall not be construed to limit the scopeof the claims. The operations and structures disclosed herein may beimplemented in a number of ways, and such changes and modifications maybe made without departing from this invention and its broader aspects.Other aspects, inventive features, and advantages of the invention, asdefined solely by the claims, are described in the non-limiting detaileddescription set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic view of an initial stage in a method of forming agroup III-V nitride semiconductor device according to an embodiment ofthe invention;

FIG. 1B is a schematic view of a preparatory stage in a method offorming a group III-V nitride semiconductor device according to anembodiment of the invention;

FIGS. 1C and 1D are schematic views illustrating a photo-assistedelectrochemical process implemented in a method of forming a group III-Vnitride semiconductor device according to an embodiment of theinvention;

FIG. 1E is a schematic view illustrating a rapid thermal annealingprocess in a method of forming a group III-V nitride semiconductordevice according to an embodiment of the invention; and

FIG. 1F is a schematic view illustrating the formation of a gateelectrode and ohmic contact layers in a method of forming a group III-Vnitride semiconductor device according to an embodiment of theinvention.

DETAILED DESCRIPTION OF THE EMBODIMENT(S)

The present application describes a method of forming a gate insulatormade of an oxide compound in the manufacture of a semiconductor device.In the embodiments herein, gallium oxide is described as a particularinstance of the oxide compound since gallium oxide can be advantageouslyused as gate insulator for GaN-based semiconductor transistors, one typeof III-V nitride semiconductor device developed in electronic andoptoelectronic applications. However, the processing steps describedherein are generally intended to be applicable for forming oxidecompounds from any group III-V nitride semiconductor elements.

In the description hereafter, a group III-V nitride semiconductorelement means GaN, InGaN, AlGaN, InAlGaN or the like.

FIG. 1A˜1F are schematic views describing a method of forming a groupIII-V nitride semiconductor device according to an embodiment of theinvention. FIG. 1A illustrates an intermediate starting stage in which abuffer layer 202 and an n-type group III-V nitride semiconductor layer204 are formed on a substrate 200. In the illustrated embodiment, thebuffer layer 202 can be exemplary made of GaN deposited by a metalorganic chemical vapor deposition process on a sapphire substrate 200,while the layer 204 can be an n-type GaN layer doped with siliconimpurities. The n-type GaN layer 204 can be configured as an activeregion where electron and hole channeling occurs in the operation of thesemiconductor device.

FIG. 1B is a schematic view illustrating the preparation of thesubstrate for a photo-assisted electrochemical process according to anembodiment of the invention. A cathode pattern 206 is formed on thesurface of the n-type GaN layer 204 to serve as cathode contact layersin the photo-assisted electrochemical process. The uncoated GaN portionserves as a local anode to facilitate the oxidation of GaN in thephoto-assisted electrochemical process. In an embodiment, the cathodepattern 206 can include aluminum formed by evaporation deposition.

FIG. 1C illustrates a photo-assisted electrochemical process performedaccording to an embodiment of the invention to grow a layer of galliumoxide Ga₂O₃ over a GaN layer. The substrate 200 is immersed in anelectrolyte bath 232 while the cathode pattern 206 is electricallyconnected via a wire 234 to an electrometer 236. Reference electrode 238and counter electrode 240, being connected via wires 234 to theelectrometer 236, are also immersed in the electrolyte bath 232. Thereference electrode 238 provides a reference voltage from which apotential bias between the substrate 200 and electrolyte bath 232 can becontrolled. For an n-type nitride layer to be immersed in theelectrolyte, the potential bias can be disconnected while theelectrolyte includes buffered acetic acid (CH₃COOH).

The electrolyte bath 232 includes a liquid solution of acetic acid(CH₃COOH) buffered with CH₃COONH₄ to an electrolyte pH value in ageneral range between about 5.5 and 7.5. In one implemented embodiment,CH₃COOH and CH₃COONH₄ can be specifically combined so as to obtain anelectrolyte pH between about 6.3 and 6.5. The substrate 200 is immersedin the electrolyte bath 232 while mercury light 242 of a wavelengthbetween about 250 nm and 260 nm, exemplary 253.7 nm in one embodiment,is irradiated on the substrate 200. The time of immersion depends on thedesired thickness of gallium oxide to be formed. In an example ofimplementation, for a substrate irradiated with a 253.7 nm mercury lightof 10 mW/cm² intensity, the oxidation rate of n-type GaN layer immersedin a buffered acetic acid CH₃COOH electrolyte of pH=6.3 can be about 15nm/min; in this embodiment, a cathode pattern of plural aluminum thinlines with 50 μm width, 100 nm thickness, and 400 μm spacing areexemplary evaporated onto the GaN surface.

Referring to FIG. 1D, the photo-assisted electrochemical process grows agallium oxynitride layer 208 (generally represented by the expressionGaO_(x)N_(y)) and a gallium oxide layer 210 over the n-type GaN layer204, wherein the gallium oxynitride layer 208 is formed at the interfacebetween the n-type GaN layer 204 and the gallium oxide layer 210. Thegallium oxynitride layer 208 and gallium oxide layer 210 compose agate-insulating layer 212.

Measure by x-ray photoemission spectrometer shows that the galliumoxynitride layer 208 has a graded composition varying from aboutGaO_(0.18)N_(0.82) in proximity of the n-type GaN layer 204 to aboutGaO_(0.82)N_(0.18) in proximity of the gallium oxide layer 210. Thisgraded composition configures the gallium oxynitride layer 208 as astrain-relief layer that promotes the growth of gallium oxide during thephoto-assisted electrochemical process.

Referring to FIG. 1E, after the photo-assisted electrochemical processis completed, the substrate 200 is dehydrated at a temperature of about400° C. for one hour. Subsequently, rapid thermal annealing (RTA) thenis conducted in O₂ environment at a temperature between about 500° C.and 800° C. for 5 minutes. The temperature of the RTA process is aprincipal factor determining the final thickness of the galliumoxynitride layer 208. In one embodiment, the thickness of the galliumoxynitride layer 208 obtained after rapid thermal annealing is betweenabout 20 nm and 30 nm, while the total thickness of the gate-insulatinglayer 212 is between about 150 nm and 200 nm. The relatively thingallium oxynitride layer 208 contributes to relieve the large latticemismatch (about 56%) between the gate-insulating layer 212 and then-type GaN layer 204, and thereby provide improved capacitance andelectrical performance.

Referring to FIG. 1F, after the gate-insulating layer 212 is formed, thecathode pattern 206 is removed. A gate electrode 214 is formed on thegate-insulating layer 212, while ohmic electrodes 216, 218 are formed ona surface of the n-type GaN layer 204 apart from the gate electrode 214to complete the structure of the transistor device. The gate electrode214 and ohmic electrodes 216, 218 can be formed via adequately etchingthe gate-insulating layer 212 followed with depositing metallicmaterials including Al, Ti, Pt, Au or the like. Suitable metallicdeposition techniques can include a deposition by evaporation,sputtering, plating or the like.

Tests on the semiconductor device formed according to the aforementionedmethodology show that it exhibits improved characteristics. Inparticular, the gate-insulating layer has a forward breakdown fieldhigher than 15 MV/cm, and a low interface state density of about 2×10¹¹cm⁻²-eV⁻¹. These factors contribute to eliminate gate leakage and allowstable high power operating voltages of the semiconductor device.

The person skilled in the art of gallium-based semiconductor manufacturewill appreciate that many variations of the invention as described abovecan be envisioned. In another embodiment not illustrated, the ohmiccontact layers can be formed, for example, via leaving portions of thecathode pattern used during the photo-assisted electrochemical processinstead of conducting a deposition step of metals.

Though the embodiments herein specifically illustrate the manufacture ofa group III-V nitride semiconductor device, the methodology describedherein for forming the gate insulator may be also applicable in themanufacture of other types of semiconductor devices such asmetal-insulator semiconductor devices or metal-oxide semiconductordevices.

Realizations in accordance with the present invention therefore havebeen described in the context of particular embodiments. Theseembodiments are meant to be illustrative and not limiting. Manyvariations, modifications, additions, and improvements are possible.Accordingly, plural instances may be provided for components describedherein as a single instance. Structures and functionality presented asdiscrete components in the exemplary configurations may be implementedas a combined structure or component. These and other variations,modifications, additions, and improvements may fall within the scope ofthe invention as defined in the claims that follow.

1. A method of forming a gallium nitride semiconductor device,comprising: forming an n-type gallium nitride layer over a substrate;conducting a photo-assisted electrochemical process to form agate-insulating layer on the n-type gallium nitride, wherein thegate-insulating layer includes gallium oxide and gallium oxynitride witha graded composition; performing a thermal annealing process; andforming a gate electrode on the gate-insulating layer.
 2. The methodaccording to claim 1, wherein conducting the photo-assistedelectrochemical process includes immersing the substrate in anelectrolyte bath including buffered acetic acid (CH₃COOH).
 3. The methodaccording to claim 2, wherein the acetic acid (CH₃COOH) is buffered withCH₃COONH₄.
 4. The method according to claim 2, wherein the electrolytebath has a pH value between about 5.5 and 7.5.
 5. The method accordingto claim 2, wherein performing a photo-assisted electrochemical processincludes emitting a radiation light with a wavelength between about 250nm and 260 nm through the electrolyte bath.
 6. The method according toclaim 1, wherein the thermal annealing process is performed at atemperature between about 500° C. and 800° C.
 7. The method according toclaim 1, wherein the thermal annealing process is performed in O₂environment.
 8. The method according to claim 1, wherein the gradedcomposition varies from about GaO_(0.18)N_(0.82) to GaO_(0.82)N_(0.18).9. The method according to claim 1, wherein the gallium oxynitride isformed with a layer thickness between about 20 nm and 30 nm.